Wafer level packages are semiconductor components obtained by processing the surface of a wafer at the semiconductor wafer stage to form rerouting patterns. After performing predetermined processing at the wafer level, they are divided into the individual pieces. These semiconductor components are then either mounted on mother boards or stacked in a chip-on-chip configuration.
When producing such semiconductor components, the individual chips formed on the semiconductor wafer are formed with interconnects (called “rerouting”) from their electrode terminals to predetermined positions where external electrodes are formed or else the interconnects are connected by wire bonding for mounting on a mother board etc.
FIG. 6 is a view of the state where the surface of a semiconductor wafer 10 is provided with an electrical insulating layer 12 and the surface of the insulating layer 12 is formed with a rerouting pattern 16 electrically connected to an electrode terminal 14 through a via 15. The rerouting pattern is for example electrically connected at one end with the electrode terminal 14 and formed at the other end with a land portion for bonding with an external connection terminal or a bonding portion for wire bonding. Rerouting patterns 16 can be formed into any pattern on the surface of the insulating layer 12, so the rerouting patterns 16 are suitably led out from the electrode terminals 14 to arrange land portions or bonding portions.
FIG. 5 shows an example of conventional formation of rerouting patterns. It shows a plan arrangement of connecting portions between electrode terminals 14 and rerouting patterns 16. The electrode terminals 14 are formed in square shapes at constant intervals on the surface of the semiconductor wafer 10. Via holes 18 are formed in the plane of the electrode terminals 14, while conductor layers at the inside of the via holes 18 are formed as vias. Via pads 20 are formed with certain widths at the peripheral rims of the via holes 18. These are to ensure the electrical connection between the rerouting patterns 16 and the vias.
Recent semiconductor chips, however, are becoming smaller in size and increased in number of terminals, so the problem has been arising that the interval of arrangement between the electrode terminals 14 has become narrower and sufficient space S between adjoining via pads 20 can no longer be obtained. In the example shown in FIG. 5, the diameter dimension R of the via pads 20 is set larger than the width dimension of the electrode terminals 14, but when the interval of arrangement between electrode terminals 14 becomes narrower, it is possible to secure the interval of arrangement between via pads 20 by making the via holes 18 smaller and reducing the diameter dimension R of the via pads 20. Forming the via holes 18 smaller, however, gives rise to problems in the processing accuracy and the problem of a higher contact resistance. Further, if the via pads 20 are made smaller, there is the problem that the reliability of the electrical connection with the rerouting patterns 16 becomes lower.
Further, when providing bonding portions at the rerouting patterns and connecting with a mother board or other semiconductor chip by wire bonding, it becomes necessary to provide the bonding portions near the electrode terminals of the semiconductor chip. In this case, there is the problem that it is difficult to secure sufficient bonding portions near the electrode terminals when the interval of arrangement of the electrode terminals of the semiconductor chip is narrow.